Referring to FIG. 1A, a conventional implementation of a nonvolatile cell 10 in a logic process is shown. The cell 10 was described in a Journal article "An EEPROM for Microprocessors and Custom Logic", IEEE JSSC, Vol. sc-20, No. 2, April 1985, which is hereby incorporated by reference in its entirety. The nonvolatile cell 10 consists of an n-channel transistor 12, an n-channel transistor 14 and an n-channel transistor 16, which together comprise the nonvolatile element. The transistors 14 and 16 comprise the capacitor structure which generates the floating gate storage element, while the transistor 12 is a select device which has a twofold purpose. In the first instance, where the bitline terminal BL represents a memory bitline (i.e., a common terminal shared by many memory cells, maybe 1000 or more), small leakage currents in unselected cells can add together to disrupt the small read current obtained from the selected cell resulting in an invalid read. In the second instance, again where the bitline terminal BL is shared between many cells, during programming or erasing, an unintentional programming of unselected cells may occur when the terminal BL is selected (depending upon the chosen bias conditions during program mode).
In the configuration described in the IEEE JSSC paper, the cell was configured as a memory array element. The advantage of the cell 10 was that it could be fabricated without significant changes from a standard CMOS logic process. A standard process may provide advantages in cost and yield (i.e., a lower number of masks and a lower time required to fabricate the device as compared with a stacked gate nonvolatile technology).
In a portion of the cell 10 shown in FIG. 1B, a thin oxide layer is shown over the drain region of the transistor 14. Programming and erase takes place in the specially fabricated thin oxide area that has a thickness less than 100 Angstroms, required for Fowler Nordheim (FN) tunneling. FN tunneling is a quantum-mechanical effect which allows electrons to pass through the energy barrier at the silicon-silicon dioxide interface. The energy required for the electrons to pass this barrier is much lower than the energy required for hot electron injection programming. This special tunnel oxide area requires an additional mask during fabrication. Programming and erasing are accomplished by Fowler Nordheim tunneling. Programming for the cell 10 in FIG. 1 was accomplished by raising the control gate terminal to a high voltage (&gt;10V) while the drain terminal is kept at 0V (the terminal BL at 0V, the terminal WL at Vcc). Under programming conditions, electrons tunnel through the thin oxide window from the substrate to the floating gate creating a negative charge on the floating gate, raising the apparent threshold voltage at the terminal CG.
During an erase, the terminal CG is grounded, the terminal BL and the terminal WL are raised to high voltage (say 10V). This sets the drain terminal D to approximately 8V (10V-Vtn). Under these conditions, electrons tunnel through the thin oxide window from the floating gate into the substrate, creating a positive charge on the floating gate. This lowers the apparent threshold voltage at the terminal CG. During a read the terminal CG and the terminal WL are set to Vcc, while the terminal BL is set to a lower voltage to prevent read disturb of the cell state but sufficient to enable a small read current to flow which may be sensed by other sense circuitry (say 0.1V to 1V).
The cell 10 has the disadvantage that it generally requires an additional mask (for the tunnel oxide layer) and requires large terminal voltages, which introduces a risk of breakdown for the n-channel junctions during programming/erase. Additionally, erasing can only be accomplished with the drain terminal D at a high voltage.